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1100 mhz variable gain amplifiers and baseband programmable filters data sheet ADRF6518 rev. 0 document fee dback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way , p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features matched pair of programmable filters and triple vgas continuous gain control range: 72 db digital gain control: 30 db filter bypass mode b andwidth (bw) 1 db g ain f latness: 300 mhz ? 3 db s mall s ignal b andwidth : 6 50 mhz/ 11 00 mhz , vga2 and vga3 21 db/12 db , respectively 6- pole butterworth filter: 1 mhz to 63 mhz in 1 mhz steps, 0.5 db corner frequency peak detector imd3: > 65 dbc for 1.5 v p - p composite output hd 2 , hd 3 : > 65 dbc for 1.5 v p - p output differential input and output flexible output and i nput common - mode ranges optional dc output offset correction spi programmable filter corners and gain steps single 3.3 v supply operation w ith power - down feature applications point - to - point and point - to - multipoint radios baseband iq receivers diversity rec eivers adc drivers instrumentation medical functional block dia gram figure 1 general description the ADRF6518 is a matched pair of fully differential low noise an d low distortion programmable filters and variable gain ampli fiers (vgas). each channel is capable of rejecting large out - of - band interferers while reliably boosting the wanted signal, thus reducing the bandwidth and resolution requirements on the analog -to- digital converters (adcs). the excellent matching between channels and their high spurious - free dynamic range over all gain and bandwidth settings make the ADRF6518 ideal for quadrature - base d (iq) communication systems with dense constellations, multiple carriers, and nearby interferers. the various amplifier gains, filter corners and other features are all programmable via a serial port interface ( spi ) port. the first vga that precedes the f ilters offers 24 db of continuous gain control with fixed gain options of 9 db, 12 db, and 15 db , and sets a differential input impedance of 400 . the filters provide a six - pole butterworth response with 0.5 db corner frequencies from 1 mhz to 63 mhz in 1 mhz steps. for operation beyond 63 mhz, the filter can be disabled and complete ly bypassed , thereby extending the ? 3 db bw up to 11 00 mhz . a wide band peak detector is available to monitor the peak signal at the filter inputs. the pair of vgas that follow the filters each provide s 24 db of continuous gain control with fixed gain options of 12 db, 15 db, 18 db, and 21 db. the output buffers offer a n additional option of 3 db or 9 db gain and provide a differential output impedance of less than 10 ?. they are cap able of driving 1.5 v p - p into 400 ? loads at better than 65 dbc hd3. the output common - mode voltage defaults to vps/2 and can be adjusted down to 900 mv via the vocm pin. independent, built - in dc offset correction loops for each channel can be disable d via the spi if fully dc - coupled operation is desired. the high - pass corner frequency is deter mined by external capacitors on the ofs 1 and ofs 2 pins and the postfilter vga gain. the ADRF6518 operates from a 3.15 v to 3.45 v supply and consumes a maximum supply current of 400 ma. when fully disabled, it consumes <1 ma. the ADRF6518 is fabricated in an advanced silicon - germanium bicmos process and is available in a 32- lead, exposed pad lfcsp. performance is specified over the ? 40 c to + 85 c temperature range. enbl vpsd comd le clk data sdo/rst vicm/ac vpi opp1 opm1 com vgn3 vocm com opm2 opp2 inp1 inm1 vps ADRF6518 ravg vgn1 ofs1 vps com inp2 inm2 vps vpk vgn2 ofs2 vps spi 11449-001
ADRF6518 data sheet rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 filter mode .................................................................................... 8 bypass mode ............................................................................... 16 mixed power and filter modes ................................................. 18 characterization ............................................................................. 19 noise figure calculation ........................................................... 19 register map and codes ................................................................ 20 theory of operation ...................................................................... 21 input vgas ................................................................................. 21 peak detector .............................................................................. 22 programmable filters ................................................................. 22 variable gain amplifiers (vgas) ............................................ 23 output buffers/adc drivers ................................................... 23 dc offset compensation loop ................................................ 23 programming the ADRF6518 ................................................... 23 noise characteristics ................................................................. 24 dis tortion characteristics ......................................................... 24 maximizing the dynamic range ............................................. 25 key parameters for quadrature - based receivers .................. 25 applications information .............................................................. 26 basic connections ...................................................................... 26 supply decoupling ..................................................................... 26 input signal path ........................................................................ 26 output signal path ..................................................................... 26 dc offset compensation loop enabled ................................ 26 common - mode bypassing ....................................................... 27 serial port connections ............................................................. 27 enable/disable function ........................................................... 27 gain pin decoupling ................................................................. 27 peak detector connections ...................................................... 27 error vector magnitude (evm) performance ........................... 27 evm test setup .......................................................................... 27 evm measurement .................................................................... 27 evm system measurement ....................................................... 29 effect of filter bw on evm ...................................................... 31 pull - down resistors for disable function ............................. 31 instability at high gain in filter bypass mode ...................... 31 l inear operation of the ADRF6518 ......................................... 32 evaluation board ............................................................................ 33 evaluation board control software ......................................... 33 schematics and artwork ........................................................... 34 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39 revision history 6/13 revision 0: initial version
da ta sheet ADRF6518 rev. 0 | page 3 of 40 specifications vps , vpi, vpsd = 3.3 v, t a = 25c, z load = 400 ?, power mode bit ( b9 ) = 0 (low power mode) , digital gain code bits ( b 8 to b2) = 0000001, and dc offset disable bit ( b1 ) = 0 (enabled) , unless otherwise noted. table 1. parameter test conditions/comments min typ max unit frequency response, filter bypass mode 1 db gain flatness bandwidth 300 mhz ? 3 db small signal bandwidth vga 2 and vga 3 21 db digital gain setting 650 mhz vga 2 and vga 3 12 db digital gain setting 1100 mhz frequency response low - pass corner frequency, f c six - pole butterworth filter, 0.5 db bandwidth 1 63 mhz step size 1 mhz corner frequency absolute accuracy over operating temperature range 8 % f c corner frequency matching channel a and channel b at same gain and bandwidth settings 0.5 % f c pass - band ripple 0.5 db p -p gain matching channel a and channel b at same gain and bandwidth settings 0.1 db group delay variation from midband to peak corner frequency = 1 mhz 135 ns corner frequency = 30 mhz 11 ns group delay matching channel a and channel b at same gain corner frequency = 1 mh z 5 ns corner frequency = 30 mhz 0.2 ns stop - band rejection relative to pass band 2 f c 30 db 5 f c 75 db input stage inp1, inm1, inp2, inm2, vicm /ac maximum input swing at minimum gain, vgn 1 = 0 v 5.0 v p -p differential inpu t impedance 400 input common - mode range , dc - coupled mode 1.5 v p - p input voltage, hd3 > 65 dbc (vpi = 3.3 v) , vicm/ac floating or logic high 1.35 1.95 v 1.5 v p - p input voltage, hd3 > 65 dbc (vpi = 5.0 v), vicm/ac floating or logic high 1.35 3.1 v input common - mo de, ac - coupled mode vpi = 3.3 v to 5.0 v, vicm/ac = 0 v vps/2 v vicm/ac input impedance 7.75 k peak detector vpk, ravg , sdo/rst output s caling relative to peak voltage at filter input 1 v/v peak reset threshold logic high duration > 25 ns >2.0 v gain control vgn 1 , vgn 2 , vgn 3 gain range maximum digital gains ?6 +66 db minimum digital gains ?36 +36 db voltage attenuation range each attenuator; v gain from 0 v to 1 v ?24 0 db gain slope 30 mv/db gain error v gain from 300 mv t o 800 mv 0.2 db output stage opp 1 , opm 1 , opp 2 , opm 2 , vocm maximum output swing at maximum gain, r load = 400 3 v p -p hd2 > 65 dbc, hd3 > 65 dbc, r load = 400 1.5 v p - p differential output impedance <10 output dc offset inputs shorted, offset loop enabled <20 mv output common - mode range 1.5 v p - p output voltage 0.9 vps ? 1.2 v vocm left floating vps/2 v vocm input impedance 23 k
ADRF6518 data sheet rev. 0 | page 4 of 40 parameter test conditions/comments min typ max unit noise/distortion corner frequency = 63 mhz output noise density minimum gain at f c /2 ?104.6 dbv/hz maximum gain at f c /2 ?104.3 dbv/hz second harmonic, hd 2 16 mhz fundamental, 1. 5 v p - p o utput level gain = 6 db 65 dbc gain = 54 db 65 dbc third harmonic, hd 3 16 mhz fundamental, 1. 5 v p -p o utput level gain = 6 db 82 dbc gain = 54 db 81 dbc imd3 30 mhz and 31 mhz tones, 1. 5 v p - p o utput l evel gain = 0 db 60 dbc gain = 30 db 80 dbc gain = 60 db 80 dbc digital logic le, clk, data, sdo input high voltage, v h igh >2 v input low voltage, v l ow <0.8 v input current, i h igh /i l ow <1 a input capacitance, c in 2 pf spi timing le, clk, data, sdo f clk 1/t clk 20 mhz t dh data hold time 5 ns t ds data setup time 5 ns t lh le hold time 5 ns t ls le setup time 5 ns t pw clk hi gh pulse width 5 ns t d clk to sdo delay 5 ns power and enable vps, vpsd, com, comd, enbl supply voltage range 3.15 3.3 3.45 v total supply current enbl = 3.3 v maximum bw setting, high power filter 400 ma minimum bw setting, low power filter 360 ma filter b ypassed, high power mode 260 ma filter b ypassed, low power mode 230 ma disable current enbl = 0 v , with pull - down resistors on output 1 ma disable threshold 1.6 v enable response time delay following enbl low - to -h igh transition 20 s disable response time delay following enbl high -to - low transition 300 ns
da ta sheet ADRF6518 rev. 0 | page 5 of 40 timing diagrams figure 2 . write mode timing diagram figure 3 . read mode timing diagram 11449-002 write bit msb - 2 lsb + 1 lsb t dh t ds t lh t ls t pw t clk clk le data lsb + 2 msb ? 1 msb lsb + 3 msb ? 3 msb ? 2 notes 1. the first data bit determines whether the part is writing to or reading from the internal 16-bit register. for a write operation, the first bit should be a logic 1. the 16-bit word is then registered into the data pin on consecutive rising edges of the clock. 11449-003 t lh t dh t ds t ls t pw t clk dc dc read bit dc dc dc dc dc lsb + 1 lsb clk le data sdo t d lsb + 2 lsb + 3 msb ? 3 msb ? 2 msb ? 1 msb dc dc notes 1. the first data bit determines whether the part is writing to or reading from the internal 16-bit register. for a write operation, the first bit should be a logic 1. the 16-bit word is then registered into the data pin on consecutive rising edges of the clock.
ADRF6518 data sheet rev. 0 | page 6 of 40 absolute m aximum ratings table 2. parameter rating supply voltages, vps, vpsd 3.45 v vpi 5.25 v enbl, le, clk, data, sdo vpsd + 0.5 v inp 1 , inm 1 , inp2 , inm 2 , vicm vps + 0.5 v opp 1 , opm 1 , opp 2 , opm 2 , vocm vps + 0.5 v ofs1, ofs2, vpk, ra vg vps + 0.5 v vgn 1 , vgn 2 , vgn 3 vps + 0.5 v internal power dissipation 1.25 w ja (exposed pad soldered to board) 37.4 c/w maximum junction temperature 150c operating temperature range ?40 c to + 85c storage temperature range ?65 c to + 150c lead t emperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicat ed in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
da ta sheet ADRF6518 rev. 0 | page 7 of 40 pin configuration and function descripti ons figure 4 . pin configuration table 3 . pin function descriptions pin o. mnemonic description 1 vpsd digital positive supply voltage: 3.15 v to 3.45 v. 2 comd digital common. connect this pin to an external circuit common using the lowest possible impedance. 3 le latch enable. spi programming pin. ttl levels: v low < 0.8 v, v high > 2 v. 4 clk spi port clock. ttl levels: v low < 0.8 v, v high > 2 v. 5 data spi data input. ttl levels: v low < 0.8 v, v high > 2 v. 6 sdo /rst spi data output (sdo). ttl levels: v low < 0.8 v, v high > 2 v. peak detector reset (rst). a > 25 ns high pulse is required on this pin to reset the detector. 7 vicm /ac input common - mode reference (vicm). vpi/2 reference output for optimal common - mode level to dri ve the differential inputs. if this pin is used as a common - mode reference for the common - mode output of the previous stage, only connect high impedance nodes to this pin. ac coupling/internal bias activation (ac). pull this pin low for ac coupling of the inputs. 8 vpi input stage supply voltage: 3.15 v to 5.25 v. connect vpi to vps if the input common - mode range is narrow ( 1.35 v to 1.95 v). connect vpi to 5 v if a common - mode input up to 3.1 v is desired. 9, 19, 22 com analog common. connect com to an e xternal circuit common using the lowest possible impedance. 10 , 11 , 30 , 31 inp 2 , inm 2 , inm 1 , inp 1 differential inputs, 400 differential input impedance. 12, 16, 25, 29 vps analog positive supply voltage: 3.15 v to 3.45 v. 13 vpk peak detector output. scaling of 1 v/v p eak differential at filter inputs is performed, and the bigger peak of two channe ls is reported. 14, 21, 27 vgn2, vgn 3, vgn 1 vga 1, vga2, and vga3 analog gain control. 0 v to 1 v, 30 mv/db gain scaling. 15, 26 ofs 2 , ofs1 offset correction loop compensation capacitors. connect capacitors to a circuit common. 17, 18, 23, 24 opp2, opm2, opm 1 , opp 1 differential outputs. these outputs have a <10 output impedance. common - mode range is 0.9 v to vps ? 1.2 v; default is vps/ 2. 20 vocm output common - mode setpoint. vocm defaults to vps/2 if left open. 28 ravg peak detector time - constant resistor. connect this pin to vps. leave this pin open for the longest hold time. the ravg range is to 1 k . 32 enbl chip enable. pull this pin high to enable the chip. ep exposed ground pad. connect the exposed pad to a low impedance ground pad. vpsd comd le clk data sdo/rst vicm/ac vpi opp1 opm1 com vgn3 vocm com opm2 opp2 com inp2 inm2 vps vpk vgn2 ofs2 vps enbl inp1 inm1 vps ravg vgn1 ofs1 vps top view (not to scale) ADRF6518 notes 1. connect the exposed paddle to a low impedance ground pad. 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 1449-004
ADRF6518 data sheet rev. 0 | page 8 of 40 typical performance characteristics f ilter mode vps , vpi, vp sd = 3.3 v, t a = 25c, z load = 400 ?, power mode bit ( b9 ) = 0 ( low power mode) , digital gain code bits ( b8 to b2) = 1111110 , dc offset disable bit ( b1 ) = 0 (enabled) , filter corner = 63 mhz, ac coupling mode, fundamental at 31 mhz, unless otherwise noted. f or hd2 / hd3 vs. g ain plots : 1.5 v p - p output target level , and refe rence figure 67 for analog gain distribution. figure 5 . in - band gain vs. vgn 1 over supply and temperature figure 6 . in- band gain vs. vgn 2 over supply and temperature figure 7 . in- band gain vs. vgn 3 over supply and temperature figure 8 . gain error vs. vgn1 over supply and temperature figure 9 . gain error vs. vgn2 over supply and temperature figure 10 . gain error vs. vgn3 over supply and temperature 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 gain (db) vgn1 (v) ?40c, vps = 3.15v, 3.3v, 3.45v +25c, vps = 3.15v, 3.3v, 3.45v +85c, vps = 3.15v, 3.3v, 3.45v 1 1449-005 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 gain (db) vgn2 (v) ?40c, vps = 3.15v, 3.3v, 3.45v +25c, vps = 3.15v, 3.3v, 3.45v +85c, vps = 3.15v, 3.3v, 3.45v 1 1449-006 0 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 gain (db) vgn3 (v) ?40c, vps = 3.15v, 3.3v, 3.45v +25c, vps = 3.15v, 3.3v, 3.45v +85c, vps = 3.15v, 3.3v, 3.45v 1 1449-007 4 ?4 ?3 ?2 ?1 0 1 2 3 0 100 200 300 400 500 600 700 800 900 1000 gain error (db) vgn1 (mv) ?40c, vps = 3.15v, 3.3v, 3.45v +25c, vps = 3.15v, 3.3v, 3.45v +85c, vps = 3.15v, 3.3v, 3.45v 1 1449-008 4 ?4 ?3 ?2 ?1 0 1 2 3 0 100 200 300 400 500 600 700 800 900 1000 gain error (db) vgn2 (mv) ?40c, vps = 3.15v, 3.3v, 3.45v +25c, vps = 3.15v, 3.3v, 3.45v +85c, vps = 3.15v, 3.3v, 3.45v 1 1449-009 4 ?4 ?3 ?2 ?1 0 1 2 3 0 100 200 300 400 500 600 700 800 900 1000 gain error (db) vgn3 (mv) ?40c, vps = 3.15v, 3.3v, 3.45v +25c, vps = 3.15v, 3.3v, 3.45v +85c, vps = 3.15v, 3.3v, 3.45v 1 1449-010
da ta sheet ADRF6518 rev. 0 | page 9 of 40 figure 11 . gain vs. frequency over vgn1/ vgn 2/ vgn 3 figure 12 . digital gain vs. frequency; vgn1/vgn2/vgn3 = 0 v figure 13 . gain mismatch between channels vs. vgn1/vgn2/vgn3 voltage figure 14 . op1db vs. gain at a fun damental of 16 mhz figure 15 . frequency response over supply and temperatur e; vgn1/vgn2/vgn3 = 0 v , filter corners = 15 mhz , 30 mhz , and 60 mhz figure 16 . gain vs. frequency over bw setting ( linear ); vgn1/vgn2/vgn3 = 0 v 60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 5 75 65 55 45 35 25 15 gain (db) frequency (mhz) 1 1449-0 11 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 55 60 gain (db) frequency (mhz) digital gain = 1111110 digital gain = 0111110 digital gain = 0011110 digital gain = 0010110 digital gain = 0001110 digital gain = 0000110 digital gain = 0000100 digital gain = 0000010 digital gain = 0000000 digital gain = 0000001 bandwidth = 63 mhz 11449-012 0/0/0 0.2/0/0 0.4/0/0 0.6/0/0 0.8/0/0 1/0/0 1/0.2/0 1/0.4/0 1/0.6/0 1/0.8/0 1/1/0 1/1/0.2 1/1/0.4 1/1/0.6 1/1/0.8 1/1/1 0.3 ?0.3 ?0.2 ?0.1 0 0.1 0.2 gain mismatch (db) vgn1/vgn2/vgn3 (v) 11449-013 15 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 ?10 50 40 30 20 10 0 op1db (dbv) gain (db) digital gain = 0000001 digital gain = 111110 11449-014 ?30 ?50 ?45 ?40 ?35 3 103938373635343332313 gain (db) frequency (mhz) 11449-015 ?40c, vps = 3.15v, 3.3v, 3.45v +25c, vps = 3.15v, 3.3v, 3.45v +85c, vps = 3.15v, 3.3v, 3.45v 40 35 30 25 20 15 10 5 0 ?5 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 gain (db) frequency (mhz) 11449-016
ADRF6518 data sheet rev. 0 | page 10 of 40 figure 17 . gain vs. frequency over bw setting (linear) ; scaled to show peaking figure 18 . gain vs. frequency over bw setting ( log ); vgn1 = 1 v, vgn 2 = 0.7 v , vgn 3 = 0 .75 v figure 19 . group delay vs. frequency; vgn1/vgn2/vgn3 = 0 v figure 20 . iq group delay mismatch vs. frequency (bw = 7 mhz and bw = 15 mhz) figure 21 . iq group delay misma tch vs. frequency (bw = 30 mhz and bw = 60 mhz) figure 22 . iq amplitude mismatch vs. frequency; vgn1/vgn2/vgn3 = 0 v 31 30 29 28 27 1 61 51 41 31 21 11 gain (db) frequency (mhz) 11449-017 ?10 ?5 0 5 10 15 20 25 30 35 40 1 10 100 gain (db) frequenc y (mhz) 11449-117 0 10 20 30 40 50 60 70 80 90 100 2 20 group delay (ns) frequency (mhz) bandwidth = 7mhz bandwidth = 15mhz bandwidth = 30mhz bandwidth = 60mhz 11449-118 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2 4 6 8 10 12 14 16 18 20 22 24 grou p del ay (ns) frequenc y (mhz) bandwi dth = 7m hz bandwid th = 15 m hz 11449-119 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 grou p del ay mism a tch (ns) frequenc y (mhz) 11449-120 5 15 25 35 45 55 65 bandwidth = 60 m hz bandwidth = 30 m hz ?0.50 ?0.40 ?0.30 ?0.20 ?0.10 0.00 0.10 0.20 0.30 0.40 0.50 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1.0 1.2 misma tch (db) frequenc y (mhz) frequenc y (mhz) bandwidth = 1 m hz bandwidth = 63 m hz 11449-121
da ta sheet ADRF6518 rev. 0 | page 11 of 40 figure 23 . noise figure vs . vgn1 over vga1 digital gain; noise density measured at half of filter corner figure 24 . noise figure vs . vgn1 over filter corner ; digital gain = 0000001, noise density measured at half of filter corner figure 25 . output noise density vs. vgn1 over v ga1 digital gain; noise density measured at half of filter corner figure 26 . output noise density vs. vgn1 over bandwidth setting; digital gain = 0000001, noise density measured at half of filter corner figure 27 . output noise den sity vs. frequency; filter corner = 7 mhz, digital gain = 0000001, noise density measured at half of filter corner figure 28 . output noise dens ity vs. frequency; filter corner = 60 mhz, digita l gain = 0000001 50 45 40 35 30 25 20 15 0 0 1000900800700600500400300200100 noise figure (db) vgn1 (mv) 11449-022 15db 12db 9db 55 50 45 40 35 30 25 20 15 10 0 1000900800700600500400300200100 noise figure (db) vgn1 (mv) 11449-023 63mhz 32mhz 16mhz 8mhz 4mhz 2mhz ?100 ?101 ?102 ?103 ?104 ?105 ?106 ?107 ?108 ?109 ?110 0 1000900800700600500400300200100 output noise density (dbv/hz) vgn1 (mv) 11449-024 15db 12db 9db ?95 ?96 ?97 ?98 ?99 ?100 ?101 ?102 ?103 ?104 ?105 ?106 ?107 ?108 ?109 ?110 0 1000900800700600500400300200100 output noise density (dbv/hz) vgn1 (mv) 11449-025 63mhz 32mhz 16mhz 8mhz 4mhz 2mhz ?100 ?105 ?110 ?115 ?120 ?125 ?130 ?135 ?140 ?145 ?150 0 25.022.520.017.515.012.510.07.55.02.5 output noise density (dbv/hz) frequency (mhz) 11449-026 gain = 60db gain = 40db gain = 20db ?100 ?105 ?110 ?115 ?120 ?125 ?130 ?135 ?140 ?145 0 20018016014012010080604020 output noise density (dbv/hz) frequency (mhz) 11449-027 gain = 60db gain = 40db gain = 20db
ADRF6518 data sheet rev. 0 | page 12 of 40 figure 29 . hd2 vs . gain over supply and temperature; 16 mhz fundamental tone , digital gain = 000000 0 figure 30 . hd3 vs. gai n over supply and temperature; 16 mhz fundamental tone, d igital gain = 0000000 figure 31 . hd 2 vs . gain over supply and temperature; 16 mhz fundamental t one, digital gain = 000000 1 figure 32 . hd3 vs. gai n over supply and temperature; 16 mhz fundamental ton e, digital gain = 0000001 figure 33 . hd2 vs . gain over vocm ; 16 mhz fundamental tone , digital gain = 0000001 figure 34 . hd3 vs. gain over vocm; 16 mhz fundamental tone, digital gain = 0000001 90 80 70 60 50 40 30 20 10 0 ?12 ?6 0 6 12 18 24 30 36 42 48 54 60 hd2 at 32mhz (dbc) gain (db) +25c, vps = 3.30v +25c, vps = 3.15v +25c, vps = 3.45v +85c, vps = 3.30v +85c, vps = 3.15v +85c, vps = 3.45v ?40c, vps = 3.30v ?40c, vps = 3.15v ?40c, vps = 3.45v 1 1449-029 100 90 80 70 60 50 40 30 20 10 0 ?12 ?6 0 6 12 18 24 30 36 42 48 54 60 hd3 at 48mhz (dbc) gain (db) +25c, vps = 3.30v +25c, vps = 3.15v +25c, vps = 3.45v +85c, vps = 3.30v +85c, vps = 3.15v +85c, vps = 3.45v ?40c, vps = 3.30v ?40c, vps = 3.15v ?40c, vps = 3.45v 1 1449-129 90 80 70 60 50 40 30 20 10 0 ?6 0 6 12 18 24 30 36 42 48 54 6660 hd2 at 32mhz (dbc) gain (db) +25c, vps = 3.30v +25c, vps = 3.15v +25c, vps = 3.45v +85c, vps = 3.30v +85c, vps = 3.15v +85c, vps = 3.45v ?40c, vps = 3.30v ?40c, vps = 3.15v ?40c, vps = 3.45v 1 1449-030 100 90 80 70 60 50 40 30 20 10 0 ?6 0 6 12 18 24 30 36 42 48 54 6660 hd3 at 48mhz (dbc) gain (db) +25c, vps = 3.30v +25c, vps = 3.15v +25c, vps = 3.45v +85c, vps = 3.30v +85c, vps = 3.15v +85c, vps = 3.45v ?40c, vps = 3.30v ?40c, vps = 3.15v ?40c, vps = 3.45v 1 1449-130 90 80 70 60 50 40 30 20 10 0 ?6 0 6 12 18 24 30 36 42 48 54 6660 hd2 at 32mhz (dbc) gain (db) vocm = 0.90v vocm = 1.25v vocm = 1.65v vocm = 1.95v 1 1449-031 100 90 80 70 60 50 40 30 20 10 0 ?6 0 6 12 18 24 30 36 42 48 54 6660 hd3 at 48mhz (dbc) gain (db) vocm = 0.90v vocm = 1.25v vocm = 1.65v vocm = 1.95v 1 1449-131
da ta sheet ADRF6518 rev. 0 | page 13 of 40 figure 35 . hd2 vs . vga1 output signal level (inferred) ; 16 mhz fundamental tone, vgn2/ vgn 3 = 0 v figure 36 . hd3 vs. vga1 output signal level (inferred); 16 mhz fundamental tone, vgn2/ vgn 3 = 0 v fig ure 37 . in- band oip3 vs. gain over digital gain ; 1.5 v p- p composite output target , 30 mhz and 31 mhz tones figure 38 . in- band oip3 vs. gain over temperature; 30 mhz and 31 mhz tones , digital gain = 00 00001 figure 39 . in- band imd3 vs. composite output voltage over gain; 30 mhz and 31 mhz tones , digital gain = 1111110 figure 40 . in- band imd3 vs. composite output voltage over gain; 30 mhz and 31 mhz tones , digital gain = 0000001 90 80 70 60 50 40 30 20 10 0 hd2 at 32mhz (dbc) vga1 output signal level (v p-p) vga1 = 9db, vgn1 = 0v vga1 = 9db, vgn1 = 1v vga1 = 15db, vgn1 = 0v vga1 = 15db, vgn1 = 1v 1 1449-032 0.02 0.04 0.06 0.09 0.14 0.23 0.36 0.57 0.90 1.14 100 90 80 70 60 50 40 30 20 10 0 hd3 at 48mhz (dbc) vga1 output signal level (v p-p) vga1 = 9db, vgn1 = 0v vga1 = 9db, vgn1 = 1v vga1 = 15db, vgn1 = 0v vga1 = 15db, vgn1 = 1v 11449-132 0.02 0.04 0.06 0.09 0.14 0.23 0.36 0.57 0.90 1.14 50 40 30 20 0 ?20 10 ?10 ?20 ?10 0 10 20 30 40 50 60 oip3 (dbv) gain (db) digital gain = 0000001 digital gain = 111110 11449-035 50 45 40 35 30 25 20 15 10 5 0 ?6 0 6 12 18 24 30 36 42 48 54 6660 oip3 (dbv) gain (db) digital gain = 0000001 +25c +85c ?40c 1 1449-135 120 100 80 60 40 20 0 imd3 (dbc) composite output voltage (v p-p) 0.5 0.6 0.9 1.3 1.8 2.5 3.6 4.5 gain = 40 gain = 30 gain = 20 gain = 10 gain = 0 1 1449-036 110 100 90 80 70 60 50 40 30 20 10 0 imd3 (dbc) composite output voltage (v p-p) 0 5.04.54.03.53.02.52.01.51.00.5 gain = 66 gain = 60 gain = 50 gain = 40 gain = 30 gain = 30 gain = 20 gain = 10 gain = 0 gain = ?5 1 1449-037
ADRF6518 data sheet rev. 0 | page 14 of 40 figure 41 . out- of -band i ip2, imd2 vs. p in ove r digital gain; 115 mhz and 145 mhz tones figure 42 . out- of -band i ip3, imd3 vs. p in over digital gain; 115 mhz and 145 mhz tones figure 43 . supply current vs. filter bandwidth over digital gain and power modes figure 44 . supply current vs. filter bandwidth over digital gain and power modes figure 45 . supply current vs. filter bandwidth over temperature , digital gain , and power modes figure 46 . common - mode rejection ratio vs. frequency 50 ?170 ?150 ?130 ?110 ?90 ?70 ?50 ?30 ?10 10 30 60 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 imd2 at 30mhz (dbv) input level at 115mhz and 145mhz (dbv) 11449-141 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 2:1 slope out-of-band ip2 vga1 = 15db vga1 = 12db vga1 = 9db ?165 ?150 ?135 ?120 ?105 ?90 ?75 ?60 ?45 ?30 ?15 0 15 imd3 at 30mhz (dbv) input level at 115mhz and 145mhz (dbv) 11449-142 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 3:1 slope out-of-band iip3 vga1 = 15db vga1 = 12db vga1 = 9db 0.45 0.40 0.35 0.30 0.25 0.20 i supply (ma) filter bandwidth (mhz) 0 656055504540353025201510 5 digital gain = 1111110, low power digital gain = 1111110, high power digital gain = 0000001, low power digital gain = 0000001, high power 1 1449-040 0 656055504540353025201510 5 0.45 0.40 0.35 0.30 0.25 0.20 i supply (ma) filter bandwidth (mhz) digital gain = 1111110, low power digital gain = 1111110, high power digital gain = 0000001, low power digital gain = 0000001, high power 1 1449-140 0 656055504540353025201510 5 0.45 0.40 0.35 0.30 0.25 0.20 i supply (ma) filter bandwidth (mhz) +25c, digital gain = 1111110, low power +85c, digital gain = 1111110, low power ?40c, digital gain = 1111110, low power 1 1449-041 80 75 70 65 60 55 50 45 40 0 60 50 40 30 20 10 cmrr (db) frequency (mhz) 11449-046 gain = 20db gain = 60db
da ta sheet ADRF6518 rev. 0 | page 15 of 40 figure 47 . peak detector time domain respon se figure 48 . vga1 gain step response ; vgn2/ vgn 3 = 0.5 v, ? 24 dbv rms input signal level, c27 = 100 pf figure 49 . vga 2/ vga 3 gain step response ; vgn1 = 0.5 v, ? 4 dbv rms input signal level, c17 and c 32 = 100 pf figure 50 . peak detector output vs. v in over temperature; vgn1 = 0.5 v, vgn2 = vgn3 = 0 v figure 51 . peak detector hold time over ravg figure 52 . peak dete ctor reset time domain response 11449-047 20ns/div vpk (200mv/div) baseband output (500mv/div) 11449-048 500ns/div 20db gain step vgn1 = 200mv to 860mv (200mv/div) 25mv p-p to 250mv p-p (50mv/div) 11449-148 500ns/div 20db gain step vgn2/vgn3 = 200mv to 530mv (100mv/div) 75mv p-p to 750mv p-p (50mv/div) 10 1 0.1 0.01 peak detector output (v peak) v in (dbv) +25c +85c ?40c 11449-044 16 ?24 ?19 ?14 ?9 ?4 1 6 11 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 peak detector output (v peak) time (ms) 11449-050 open 1m 100k 11449-055 10ns/div vpk (200mv/div) sdo/rst (1v/div)
ADRF6518 data sheet rev. 0 | page 16 of 40 b ypass m ode vps = 3.3 v, t a = 25c, z load = 400 ?, power mode bit ( b9 ) = 1 (high power mode), digital gain code bits ( b8 to b2 ) = 111 1110, dc offset disable bi t ( b1 ) = 0 (enabled) , unless otherwise noted. figure 53 . frequency response over supply and temperature figure 54 . group delay vs. frequency figure 55 . output noise density vs. frequency over analog gains; digital gain = 0000001 figure 56 . noise figure vs. vgn1 over digital gain figure 57 . output noise density vs. vgn1 over digital gain figure 58 . hd2 vs. gain over temperature ; fundamental at 80 mhz , digital gain = 0000001 50 40 30 20 10 0 ?10 1m 1g 100m 10m gain (db) frequency (hz) 11449-202 digital gain = 0000001 digital gain = 1111110 vps = 3.15v, 3.3v, 3.45v +85c +25c ?40c 0 5 10 15 20 25 30 1m 10m 100m 1g grou p del ay (ns) frequenc y (hz) 11449-154 ?100 ?180 ?170 ?160 ?150 ?140 ?130 ?120 ?110 50 400 350 300 250 200 150 100 output noise density (dbv/hz) frequency (mhz) 11449-156 vgn1, vgn2, vgn3: 0v ,0v ,0v and 1v ,0v ,0v vgn1, vgn2, vgn3: 1v ,1v ,0v vgn1, vgn2, vgn3: 1v ,1v ,1v 45 40 35 30 25 20 15 0 1000900800700600500400300200100 noise figure (db) re to 50 load vgn1 (mv) 11449-158 15db 12db 9db ?110 ?111 ?112 ?113 ?114 ?115 ?116 ?117 ?118 ?119 ?120 0 1000900800700600500400300200100 output noise density (dbv/hz) vgn1 (mv) 11449-159 15db 12db 9db 1 1449-051 0 10 20 30 40 50 60 70 0 6 12 18 24 30 36 42 48 54 60 hd2 a t 160mhz (dbc) gain (db) +85 c +25 c ?40 c
da ta sheet ADRF6518 rev. 0 | page 17 of 40 figure 59 . hd3 vs. gain o ver temperature ; fundamental at 80 mhz , digital gain = 0000001 figure 60 . imd 3 vs. composite output voltage over vocm; vgn1/vgn2/vgn3 = 1 v, 125 mhz and 12 6 mhz tones figure 61 . in- band oip3 bypas s vs. gain over temperature; digital gain = 0000001 , 12 5 mhz and 12 6 mhz tones figure 62 . gain vs. frequency figure 63 . peak detector output vs. v in over temperature; vgn1 = 0.5 v, vgn2/vgn3 = 0 v ; 125 mhz tone 1 1449-052 0 10 20 30 40 50 60 70 80 90 0 6 12 18 24 30 36 42 48 54 60 hd3 a t 240mhz (dbc) gain (db) +85 c +25 c ?40 c 120 100 80 60 40 20 0 4.5 3.6 2.5 1.8 1.3 0.9 0.6 0.5 imd3 (dbc) composite output voltage (v p-p) 11449-061 gain = 40 gain = 30 gain = 20 gain = 10 gain = 0 50 40 30 20 10 0 12 18 24 30 36 42 48 54 6660 oip3 bypass (dbv) gain (db) +25c +85c ?40c 1 1449-056 80 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 1g 100m 10m 1m gain (db) frequency (hz) 11449-203 digital gain = 0000001 digital gain = 1111110 digital gain = 0000001 digital gain = 1111110 vgn1, vgn2, vgn3 = 1v vgn1, vgn2, vgn3 = 1v vgn1, vgn2, vgn3 = 0v vgn1, vgn2, vgn3 = 0v 10 1 0.1 0.01 16 ?24 ?19 ?14 ?9 ?4 1 6 11 peak detector output (v peak) v in (dbv) 11449-065 +25c +85c ?40c
ADRF6518 data sheet rev. 0 | page 18 of 40 mixed power and filt er m odes vps = 3.3 v, t a = 25c, z load = 400 ?, digital gain code bits ( b8 to b2 ) = 111 1110, dc offset disable bit ( b1 ) = 0 (enabled) , unless otherwise noted. figure 64 . common - mode rejecti on ratio (cmrr) vs. frequency figure 65 . channel isolation (opm1_se to opm2_se ) vs. frequency , filter mode figure 66 . channel isolation (opm1_se to opm2_se) vs. frequency, bypass mode 80 70 60 50 40 30 20 10 0 0 1000900800700600500400300200100 cmrr (db) frequency (mhz) 11449-057 gain = 20db gain = 60db gain = 40db 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 isol a tion (db) frequenc y (mhz) gain = 20 db gain = 60 db bandwidth = 63 m hz 11449-171 isol a tion (db) frequenc y (mhz) 11449-172 0 10 20 30 40 50 60 70 80 90 100 100 200 300 400 500 600 700 800 900 1000 gain = 20 db gain = 60 db bandwidth = 63 m hz
da ta sheet ADRF6518 rev. 0 | page 19 of 40 c haracterization figure 67 . gain distribution for hd2/ hd 3 vs. gain figure 67 shows the ADRF6518 analog gain distribution for the hd2 vs. gain and hd3 vs. gain plots while the gain and input voltage level s were swept and while keeping the output voltage level at 1.5 v p- p. noise figure calcula tion all of the noise figure plots (see figure 23, figure 24 , and figure 56) were completed by input referring the output noise density and then dividing it by the theoretical noise density of a 50 ? resister. the input sma on the evaluation board was terminated with a 50 ? resistor to ground, which provided the ADRF6518 input with a 400 ? differential impedance via the 8:1 balun. in sig nal chain calculations , it is often convenient to reference the noise figure to 50 ? , even though the ADRF6518 input is terminated in 400 ?. the noise factor is calculated as follows: ? = 50 n gain n factor noise out w here the noise densities are in nv/hz and gain is in linear terms. the noise figure is then noise figure = 10 log 10 ( noise factor ) 1.2 0.8 0.4 0 1.0 0.6 0.2 66 ?12 ?6 0 6 12 18 24 30 36 42 48 54 60 vgn1/vgn2/vgn3 (v) gain (db) 11449-066 solid lines, digital gain code = 0000001 dashed lines, digital gain code = 0000000 vgn1 vgn2 vgn3 vgn1 vgn2 vgn3
ADRF6518 data sheet rev. 0 | page 20 of 40 register map and cod es the filter frequency, amplifier gains, filter bypass mode , and offset correction lo ops can be programmed using the spi interface. table 5 provides the bit map for the internal 15 - bit register of the ADRF6518 . table 4 . filter mode and power mode options b9 filter bypass filter 0 vga low power; filter off vga low power; filter low power 1 vga high power; filter off vga low power; filter high power table 5 . register map msb lsb b 15 b 14 b 13 b 12 b 11 b 10 b9 b8 b7 b6 b5 b4 b3 b2 b1 filter frequency code and filter bypass mode power mode digital gain code dc offset disable code = 1 db corner in mhz for example, 31 mhz = 011111 (msb first) use 000000 for filter bypass mode 0 : low power 1: high power use 1 for filter bw > 31 mhz, in filter mode use 1 for channel bw > 60 mhz, in filter bypass mode vga1 gain 00: 15 db 01: 12 db 10: 9 db 11: 9 db vga2 gain 00: 21 db 01: 18 db 10: 15 db 11: 12 db vga3 gain 00: 21 db 01: 18 db 10: 15 db 11: 12 db postamp 0: 3 db 1: 9 db 0: enable 1: disable
da ta sheet ADRF6518 rev. 0 | page 21 of 40 theory of operation figure 68 . signal path block diagram for a single channel of the ADRF6518 the ADRF6518 consists of a matched pair of input vgas followed by programmable filters, and then by a cascade of two variable gain amplifiers and output adc drivers. the filters can be bypassed a nd powered down through the spi interface for operation beyond the maximum filter bandwidth. the block diagram of a single channel is shown in figure 68. the programmability of the filter bandwidth and of the pre fi lter - ing and post filtering fixed gains through the spi interface offers great flexibility when coping with signals of varying levels in the presence of noise and large, undesired signals near the desired band. the entire differential signal chain is dc - cou pled with flexible interfaces at the input and output. the bandwidth and gain setting controls for the two channels are shared, ensuring close matching of their magnitude and phase responses. the ADRF6518 can be fully disabled through the enbl pin. filtering and amplification are fundamental operations in any signal processing system. filtering is necessary to select the intended signal while rejecting out - of - band noise and interfer - ers. amplification increases the level of the desired signal to overcome noise added by the system. when used together, filtering and amplification can extract a low level signal of interest in the presence of noise and out - of - band interferers. such analog signal pro cessing alleviates the requirements on the analog, mixed signal, and digital components that follow. input vgas the input vgas provide a convenient interface to the sensitive filter sections that follow. they are designed to have a low noise figure and hi gh linearity. the combination of analog gain control and digital gain settings allow a wide range of input signal levels to be conditioned to drive the filters at up to 1.5 v p- p amplitude. the vgas set a differential input impedance of 400 ?. the baseband input signal can be ac - coupled or dc - coupled via pin 7 selection. when the signal is dc - coupled, the wide input common - mode voltage is supported by having an optional 5 v supply on pin 8, vpi. the d efault common - mode voltage is vpi/2, which is available o n the dual function pin 7, vicm/ac, to set the output common - mode voltage of the driving circuit . however, this is optional and input common - mode can be independently set within the supported range. for a 3.3 v supply on vpi, the input common mode can rang e from 1.35 v to 1.95 v, while maintaining a 5 v p- p input level at >60 dbc hd2 and hd3 . for a 5 v supply on vpi, the input common - mode range extends to 1.35 v to 3.1 v. extra current is drawn from the vpi supply to support an input common mode greater tha n the mid value of the main 3.3 v supply, that is, vps/2. the vicm/ac voltage is not buffered and must be sensed at a high impedance point to p revent it from being loaded down. when the baseband input signal is ac - coupled, pull the vicm/ac pin low to activa te the internal bias for the input stage. the input vgas have analog gain control of 24 db , followed by a digital gain settings of 9 db , 12 db, or 15 db , selectable through the spi (see the register map and codes section). the vgas are based on the analog devices, inc., patented x - amp? architecture, consisting of tapped 24 db attenuators , followed by programmable gain amplifiers. the x - amp architecture gener - ates a continuous linear - in - db monotonic gain response wi th low ripple. the analog gain of the vga sections are controlled through the high impedance vgn1 pin with an accurate slope of 30 mv/db. adjust t he vga analog gain through an agc mechanism, such that 1.5 v p- p at the output of the first vga is not exceede d. if , however , the input signal is small enough, the first vga can be set at full gain for best noise figure ( nf ) perfor - mance and gain control achieved in the second or third vga. driving adr f6518 single - ended the input structure of the ADRF6518 is designed for differen- tial drive. however , with some performance degra dation, it can be driven single - ended, especially at low bandwi dth signals. see the applications information s ection for guidance on single - ended drive. 9db/12db/15db 12db/15db/ 18db/21db 12db/15db/ 18db/21db 3db/9db 1mhz to 63mhz programmable filters 24db vga 24db vga 24db vga 3db/9db adc driver baseband inputs baseband outputs gain and filter programming spi bus analog gain control 30mv/db output common-mode control spi interface input common-mode control 1 1449-067
ADRF6518 data sheet rev. 0 | page 22 of 40 peak detector to measure the signal level at the critical interface of the vga1 output and the programmable filter input, a peak detector has been implemented. the peak detector simultaneously measures both channels at the vga1 output and reports the bigger of the two at the vpk pin. the on - chip holding cap acitor and negligi - ble leak age at the internal node ensure a large droo p time of the order of a m illis ec ond , which is a function of the peak voltage as well. bigger peak voltage results in longer droop time. the droop time can be adjusted down by placing a resistor between the ravg and vp s pi ns . typical values of ravg can ran ge from 1 m ? to 1 k? . as the ravg resistor value is reduced, the peak voltage , vpk, appears as an envelope output. the peak detector has the attack bandwidth of 100 mhz. the peak detector can be used in an agc loop to set the appropri - ate signal level at t he filter input. for such an implementation, f ilter vpk appropriately, considering that it is a peak hold output. a high pulse of 25 ns or longer duration applied to the sdo/rst dual function pin reset s the vpk voltage to 0 v by discharging the internal ho lding cap acitor . programmable filters the integrated programmable filter is the key signal processing function in the ADRF6518 . the filters follow a six - pole butter - worth prototype response th at provides a compromise between band rejection, ripple, and group delay. the 0.5 db bandwidth is programmed from 1 mhz to 63 mhz in 1 mhz steps via the serial programming interface (spi) as described in the programming the ADRF6518 section. the filters are designed so that the butterworth prototype filter shape and group delay responses vs. frequency are retained for any bandwidth setting. figure 69 and figure 70 illustrate the ideal six - pole butterworth response. the group delay, g , is defined as g = ??/? where: is the phase in radians. = 2 f is the frequency in radians per second. note that for a frequency scaled filter prototype, the a bsolute magnitude of the group delay scales inversely with the band - width; however, the shape is retained. for example, the peak group delay for a 28 mhz bandwidth setting is 14 less than for a 2 mhz setting. figure 69 . sixth -o rder butterworth magnitude response for 0.5 db bandwidths programmed from 2 mhz to 29 mhz in 1 mhz steps figure 70 . sixth - order butterworth group delay response for 0.5 db bandwidths programmed to 2 mhz and 28 mhz the corner freq uency of the filters is defined by rc products, which can vary by 30% in a typical process. therefore, all the parts are factory calibrated for corner frequency, resulting in a residual 8 % corner frequency variation over the ?40c to +85c temperature ra nge. although absolute accuracy requires calibration, the matching of rc products between the pair of channels is better than 1% by observing careful design and layout practices. calibration and excellent matching ensure that the magnitude and group delay responses of both channels track together, a critical requirement for digital iq - based communication systems. bypassing the filters for higher bandwidth applications, filters of the ADRF6518 can be bypassed via the spi. in the filter bypass mode, filters are disabled and power consumption is significantly reduced. the bandwidth of cascaded vgas, which is significantly larger than 63 mhz maximum of the filters, is fully realized in the filter b ypass mode. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 1m 10m 100m 1g relative magnitude (hz) frequency (hz) 1 1449-068 500 400 300 200 100 0 ?100 100k 1m 10m 100m group delay (ns) frequency (hz) bw = 2mhz bw = 28mhz 14 1 1449-069
da ta sheet ADRF6518 rev. 0 | page 23 of 40 variable gain amplif iers (vga s) the cascaded vga 2 and vga 3 are also based on the x - amp architecture, and each has 24 db gain range with separate high impedance gain control inputs , vgn2 and vgn3. the vga structures of the second and third vga s are identical to that of the first vga . however, these have slightly higher noise figure and less drive level capability. their output is rated at 1 v p- p for >60 dbc hd2 and hd3. depending on the input signal range, the second or third vga or both can b e used for agc purposes. the critical level to consider while making this choice is the signal level at the output of the vgas, which must not exceeded 1 v p- p to maintain low distortion. the fixed gain following both of the variable gain sections can also be pro grammed to 12 db , 15 db , 18 db, or 21 db to maxim - ize the dynamic range. output buffers/adc d rivers the low impedance (<10 ?) output buffers of the ADRF6518 are designed to drive either adc inputs or subsequent ampli fier stages. they are capable of delivering up to 4 v p - p composite two - tone signals into 400 ? differential loads with >60 dbc imd3. the output common - mode voltage defaults to vps/2, but it can be adjusted from 900 mv to vps ? 1.2 v without loss of drive capability by presenting the vocm pin with the desired common - mode voltage. the high input impedance of vocm allows the adc reference output to be connected directly. even though the output common - mode voltage is adjustable , and the offset compensation loop can null the accumulated dc offsets (see the dc offset compensation loop section), it may still be desirable to ac - couple the outputs by selecting the coupling capacitors according to the load imped - ance and desired bandwidth. dc offset compensati on loop in many signal processing applica tions, no information is carried in the dc level. in fact, dc voltages and other low frequency disturbances can often dominate the intended signal and consume precious dynamic range in the analog path and bits in the data converters. these dc voltages can be present with the desired input signal or can be generated inside the signal path by inherent dc offsets or other unintended signal - dependent processes such as self - mixing or rectification. because the ADRF6518 is fully dc - coupled, it may be necessary to remove these offsets to realize the maximum signal - to - noise ratio (snr). the external offsets can be eliminated with ac - coupling capacitors at the input pins ; however, that requires large val ue capacitors because the impedances can be fairly low, and high - pass corners may need to be <10 hz in some cases. to address the issue of dc offsets, the ADRF6518 provides an offset correctio n loop that nulls the output differential dc level , as shown in figure 71 . if the correction loop is not required, it can be disabled through the spi port. figure 71 . offset compensation loop operates around the vga and output buffer the offset control loop creates a high - pass corner, f hp , that is superimposed on the normal butterworth filter response when filters are enabled. typically, f hp is many orders of magnitude lower than the lower programmed filter bandwidth so that there is no interaction between them. setting f hp is accomplished with capacitors, c ofs , from the ofs1 and ofs2 pins to ground. because the correction loop works around the vga sections, f hp is also dependent on the t otal gain of the cascaded vgas. in general, the expression for f hp is given by f hp (hz) = 6.7 post filter linear gain / c ofs (f) where post filter linear gain is expressed in linear terms, not in decibels (db), and is the gain following the filters, whi ch excludes the vga 1 gain. note that f hp increases in proportion to the gain. for this reason, choose c ofs at the highest operating gain to guarantee that f hp is always below the maximum limit required by the system. programming the ADRF6518 the 0.5 db corner frequencies for both filters, the digital gains of all the vgas , and the output buffers are programmed simultane - ously through the spi port. in addition to these, enabling the dc offset co mpensation loop and power mode selection are also controlled through spi port. a 16 - bit register stores 15 data bits, including the 6 - bit code for corner frequencies of 1 mhz through 63 mhz and filter bypass, as well as the cod es for vga gains, and the pos tamplifier gain (see table 5 ). the spi protocol not only allows these selections to be written to the data pin, but also allows the stored code to be read back via the sdo/rst pin. the latch enable (le) pin must f ir s t go to a logic 0 for a read or write cycle to begin. on the next rising edge of the clock (clk), a logic 1 on the data pin initiates a write cycle, whereas a logic 0 on the data pin initiates a read cycle. in a write cycle, the next 15 clk rising edges latch the desired 15 - bit code, lsb first. this results in 16 - bit code , including the first logic 1 to initiate a write cycle. when le goes high, the write cycle is completed and different codes are presented various blocks that need programming. in a read cycle, the next 15 clk falling edges present the stored 15 - bit code, lsb first. when le goes high, the read cycle is completed. detailed timing diagrams are shown in figure 2 and figure 3 . gain from filters c ofs ofsx ofds 50db vga output adc driver baseband outputs 1 1449-070
ADRF6518 data sheet rev. 0 | page 24 of 40 noise characteristic s the output noise behavior of the ADRF6518 depends on the gain and bandwidth settings. vga1 noise dominates in the filter bypass mode and at high filte r corner settings. while at low corner settings, filter noise tends to dominate. the filter contributes a noise spectral density profile that is flat at low frequencies, peaks near the corner frequency, and then rolls off as the filter poles roll off the g ain and noise. the magnitude of the noise spectral density contributed by the fil ter, expressed in nv/hz, varies inversely with the square root of the bandwidth setting, resulting in filter noise in nv that is nearly constant with the bandwidth setting. however , with vga1 nf being lower than the filter, vga1 tends to dominate the over all nf. at higher frequencies, after the filter noise rolls off, the noise floor is set by the vgas. each of the x - amp vga sections used in the ADRF6518 contributes a fixed noise spectral density to its respective output, independent of the analog gain setting. with the digital gain change , however, vga output noise changes, because the gain setting resistors values change. as an example, the vga1 nf corresponding to a 15 db gain setting is 1 7. 3 db, whereas for a 9 db gain, the nf is 19 db. when cascaded, the total noise contributed by the vgas at the output of the ADRF6518 increases gradually with higher gain. this is apparent in t he noise floor variation at high frequencies at different vga gain settings. the exact relationship depends on the programmed fixed gain of the amplifiers. at lower frequencies within the filter bandwidth setting, the vgas translate the filter noise direct ly to the output by a factor equal to the gain following the filter. at low values of vga gain, the noise at the output is the flat spectral density contributed by the last vga. as the gain increases, more of the filter and first vga noise appears at the output. because the intrinsic filter noise density increases at lower bandwidth settings, it is more pronounced than it is at higher bandwidth settings. in either case, the noise density asymptotically approaches the limit set by the vgas at the highest frequencies. for other values of vga gain and bandwidth setting, the detailed shape of the noise spectral density changes according to the relative contributions of the filters and vgas. because the noise spectral density outside the filter bandwidth is li mited by the vga output noise, it may be necessary to use an external, fixed frequency, passive filter prior to analog - to - digital conversion to prevent noise aliasing from degrading the signal - to - noise ratio. a higher sampling rate, relative to the maxi - mu m required ADRF6518 corner frequency setting, reduces the order and complexity of this external filter. distortion characteristics to maintain low distortion through the cascaded vgas and filt er of the ADRF6518 , consider the distortion limits of each stage. t he first vga has higher signal handling capability and bandwidth than vga2 and vga 3, because it must cope with out - of - band si gnals that can be larger than the in - band signals. in the filter mode, these out - of - band signals are filtered before reaching vga 2 and vga 3. it is important to understand the signals presented to the ADRF6518 and to match these signals with the input and output characteristics of the part. it is useful to partition the ADRF6518 into the front end , composed of vga1 and the f ilter , a nd the back end , composed of vga2 and vga 3 and the o utput b uffers. vga1 can handle a 5 v p- p signal at a maximum analog attenua - tion setting , w ithout experiencing appreciable distortion at the input. in most applications, vga1 gain should be adjusted such that the maximum signal presented at the filter inputs (or vga2 input in filter bypass mode) is <1.5 v p- p. at this level , the front end does not limit the distortion performance. the p eak detector output, vpk , can be used as an indicator of the signal lev el present at this critical interface. choose t he second and third vga gains such that their output level s do not exceed 1 v p- p. if the output signal level is expected to exceed 1.5 v p- p, it is recommended to set the postamplifier gain to 9 db. for thes e signal level considerations, it is recommended that the out - of - band signal , if larger than the desired in - band signal, be addressed . in filter mode , such an out - of - band signal only affect s the vga1 operation, because it is filtered out by the filter and does not affect the following stages. in this case, a high vga2 and vg a 3 gain may be needed to raise the small desired signal to a higher level at the output. in the filter bypass mode, such out - of - band signals may need to be filtered prior to the ADRF6518 . th e overall distortion introduced by the part depends on the input drive level, including the out - of - band signals, and the desired output signal level. to achieve best distortion performance and the desired overall gain , keep in mind the maximum signal levels indicated previously when selecting differe nt vga gains . to distinguish and quantify the distortion performance of the input section, two different ip3 specifications are presented. the first is called in - band ip 3 and refers to a two - tone test where the signals are inside the filter bandwidth. this is exactly the same figure of merit familiar to communications engineers in which the third - order intermodulation level, imd 3 , is measured. to quantify the effect of out -of - band signals, a new out - of - band (oob) iip3 figure of merit is introduced. this test also involves a two - tone stimulus; however, the two tones are placed out - of - band so that the lower imd3 product lands in the middle of the fi lter pass band. at the output, only the imd3 product is visible because the original two tones are filtered out. to calculate the oob i ip3 at the input, the imd3 level is referred to the input by the overall gain. the oob iip3 allows the user to predict th e impact of out - of - band blockers or interferers at an arbitrary signal level on the in - band performance. the ratio of the desired input signal level to the input - referred imd3 at a given blocker level represents a signal - to - distortion limit imposed by the out - of - band signals.
da ta sheet ADRF6518 rev. 0 | page 25 of 40 maximizing the dynamic range when used in the filter mode, the role of the ADRF6518 is to increase the level of a variable in - band signal while minimizing out - of - band sign als. ideally, this is achieved without degrading the snr of the incoming signal or introducing distortion to the incoming signal. the first goal is to maximize the output signal swing, which can be defined by the adc input range or the input signal capacit y of the next analog stage. for the complex waveforms often encoun - tered in communication systems, the peak - to - average ratio, or crest factor, must be considered when choosing the peak - to - peak output. from the chosen output signal and the maximum gain of t he ADRF6518 , the minimum input level can be defined. as the input signal level increases, the vga3 gain is reduced from its maximum gain point to maintain the desired fixed output level. vga2 and vga 1 can then be adjusted as the input signal level keeps increasing. this maintain s the best nf for the cascaded chain. the output noise, initially dominated by the filter and vga1 combination, follows the gain reduction, yielding a progressively bett er snr. at some point, the vga 3 and vga 2 gains drop sufficiently so that their noise becomes dominant, resulting in a slower reduction in snr from that point. from the perspective of snr alone, the maximum input level is reached when the vga1 reaches its m inimum gain. distortion must also be considered when maximizing the dynamic range. at low and moderate signal levels, the output distortion is constant and assumed to be adequate for the selected output level. at some point, the input signal becomes large enough that distortion at the input limits the system. this can be kept in check by monitoring peak detector voltage, vpk. the most challenging scenario in terms of dynamic range is the presence of a large out - of - band blocker accompanying a weaker in - band wanted signal. in this case, the maximum input level is dictated by the blocker and its inclination to cause distortion. after filtering, the weak wanted signal must be amplified to the desired output level, possibly requiring the maximum gain on vga2 and vga 3. in such a case, both the distortion limits associated with the blocker at the input and the snr limits created by the weaker signal and higher gains are present simultaneously. furthermore, not only does the blocker scenario degrade the dynamic range , it also reduces the range of input signals that can be handled because a larger part of the gain range is simply used to extract the weak desired signal from the stronger blocker. key parameters for q uadrature - based receivers the majority of digital comm unication receivers make use of quadrature signaling, in which bits of information are encoded onto pairs of baseband signals that then modulate in - phase (i) and quadrature (q) sinusoidal carriers. both the baseband and modulated signals appear quite compl ex in the time domain with dramatic peaks and valleys. in a typical receiver, the goal is to recover the pair of quadrature baseband signals in the presence of noise and interfering signals after quadrature demodulation. in the process of filtering out - of - band noise and unwanted inter - ferers and restoring the levels of the wanted i and q baseband signals, it is critical to retain their gain and phase integrity over the bandwidth. in filter mode, the ADRF6518 delivers flat in - band gain and group delay, consistent with a six - pole butterworth prototype filter, as described in the programmable filters section. furthermore, careful design ensures excellent ma tching of these parameters between the i and q channels. although absolute gain flatness and group delay can be corrected with digital equalization, mismatch introduces quadrature errors and intersymbo l interference that degrade bit error rates in digital communication systems. for wideband signals, filters can be bypassed and the ADRF6518 then be comes a dual cascaded chain of three vgas, offering large gain range options , while maintaining gai n and group delay match between the two channels.
ADRF6518 data sheet rev. 0 | page 26 of 40 applications informa tion basic connections figure 72 shows the basic connections for a typical ADRF6518 applicati on. supply decoupling apply a nominal supply voltage of 3.3 v to the supply pins , vps, vpi , and vpsd . the supply voltage must not exceed 3.45 v or drop below 3.15 v for vps and vpsd . the supply voltage on vpi must not exceed 5.25 v. decouple e ach supply pi n to ground with at least one low inductance, surface - mount ceramic capacitor of 0.1 f placed as close as possible to the ADRF6518 device. the ADRF6518 has t hree separate supplies: two analog suppl ies and a digital supply. take c are to separate the analog and digital supplies with a large surface - mount inductor of 33 h. then decouple e ach supply separately to its respective ground through a 10 f capacitor. input signal path ea ch signal path has an input vga , accessed through the inp1, inm1, inp2, and inm2 pins, that set s a differential input impedance of 400 ?. the inputs can be dc - coupled or ac -coupled. to ac couple the inputs , the user must p ull the vicm/ac pin to ground. this provides an input common - mode voltage of vpi/2. to dc couple the inputs, let the vicm pin float. if using direct dc coupling, the common - mode voltage, v cm , can range from 1.35 v to 1.95 v while vpi = 3.3 v . the use r has the option of tying vpi to a voltage up to 5 v. this provides a common - mode range of 1.35 v to 3.1 v. in general, the minimum input common - mode voltage is always 1.35 v, but the maximum common - mode voltage is v cm_max = 0.64 vpi ? 0.135 v. the vicm pin can be used as a reference common - mode voltage for driving a high impedance sensing node of the preceding cascaded part (vicm has a 7.75 k? impedance). output signal path the low impedance ( 10 ?) output buffers are designed to driv e a high impedance load, such as an adc input or another amplifier stage. the output pins opp1, opm1, opp2, and opm2 sit at a nominal output common - mode voltage of vps/2, but can be driven to a voltage of 0. 9 v to vps ? 1.2 v by applying the desired common - mode voltage to the high impedance vocm pin. dc offset compensati on loop enabled when the dc offset compensation loop is enabled via b1 of the spi register, the ADRF6518 can null the output differential dc level. the loop is enabled by setting b1 = 0. the offset compensation loop creates a high - pass corner frequency, which is proportional to the value of the capacitors that are connected from the ofs1 and ofs2 pins to ground. for more information about setting the high - pass corner frequency, see the dc offset compensation loop section. figure 72 . basic connections vpsd comd le clk data sdo/rst vicm/ac vpi opp1 opm1 com vgn3 vocm com opm2 opp2 com inp2 inm2 vps vpk vgn2 ofs2 vps enbl inp1 inm1 vps ravg vgn1 ofs1 vps ADRF6518 vps vpsd 0.1f vpi vps vps vps vps output1(+) input1(?) 0.1f input1(+) input2(+) input2(?) output1(?) output2(?) output2(+) 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f serial control interface 0.1f 0.1f 0.1f 1 1449-071
da ta sheet ADRF6518 rev. 0 | page 27 of 40 common - mode bypassing decouple t he ADRF6518 common - mode pins, vicm /ac and vocm, to ground. use a t least one low inductance, surface - mount ceramic capacitor with a value of 0.1 f to decouple the common - mode pins. serial port connections the adrf 6518 has a spi port to control the gain and filter band - width settings. data can be written to the internal 15- bit register and read from the register. it is recommended that low - pass rc filtering be placed on the spi lines to filter out any high frequen cy glitches. see figure 88 , the evaluation board schematic, for an example of a low - pass rc filter. enable/disable funct ion to enable the ADRF6518 , pull the enbl pin high. driving the enbl pin low disables the device, reducing current consump - tion to approximately 1 ma at room temperature. for the disable function to work properly, connect 10 k ? pull - down r esistors from the signal output pins (opp1, opm1, opp2, opm2) to ground to allow a dc path to ground for proper discharge (s ee figure 67 ). if the disable function is not used, pull - down resistors are not necessary. g ain pin decoupling t he ADRF6518 has three analog gain control pins: vgn1, vgn2, and vgn3. use a t least one low inductance, surface - mount cerami c capacitor with a value of 0.1 f to decouple each gain control pin to ground. peak d etector c onnections t he ADRF6518 has a p eak detector outpu t on the vpk pin, with a s caling of 1 v/v p ea k differential at filter inputs. the b igger peak of the two channels is reported. the p eak detector time - constant can be changed with a resistor from the ravg pin to vps. leave t he r avg pi n open for the longest time - constant ( hold time ). the ravg resistor range is to 1 k . to reset the peak detector, pull the sdo/rst pin high for 25 ns or longer. logic levels are v low < 0.8 v, v high > 2 v. error vector magnitu de (evm) performance error vector magnitude (evm) is a measure used to quantify the performance of a digit al radio transmitter or receiver by measuring the fidelity of the digital signal transmitted or received. various imperfections in the link, such as magnitude and phase imbalance, noise, and distortion, cause the constellation points to deviate from their ideal locations. in general, a receiver exhibits three distinct evm limitations vs. received input signal power. as signal power increases, the distortion components increase. ? at large enough signal levels, where the distortion compo - nents due to the harmonic nonlinearities in the device are falling in - band, evm degrades as signal levels increase. ? at medium signal levels, where the signal chain behaves in a linear manner and the signal is well above any notable noise contributions, evm has a tendency to reach an opti - mal level determined dominantly by either the quadrature accuracy and iq gain match of the signal chain or the precision of the test equipment. ? as signal levels decrease, such that noise is a major con - tributor, evm performance vs. the signal level exhibits a decibel - for - decibel degradation with decreasing signal level. at these lower signal levels, where noise is the dominant limitation, decibel evm is directly proportional to the snr. evm test setup the basic setup to test the evm for the ADRF6518 consisted of an agilent mxg n 5182b v ector s ignal g enerator used as a signal source and a n agilent dso7104b oscilloscope used to sample t he signal while connected to a computer running agilent 89600 vector signal analysis ( vsa ) software to calculate the evm of the signal. the i and q outputs of the ADRF6518 were loaded with 400 ? differential impedances and connected differentially to two ad8130 amplifiers to c onvert the signals into single - ended signals. the single - ended signals were connected to the input channels of the vector signal analyzer . evm measurement evm was measured for the ADRF6518 only (the ad8130 amplifiers were used , but their evm contribution is minimal and do not dominate the measurement). the n 5182b iq baseband differential outputs drove the ADRF6518 inputs th r ough 1 f coupling cap acitor s. large coupling capacitors are necessary t o keep the high - pass corner created by the capacitors a s low as possible and to prevent the low - pass corner from corrupting the signal. the vicm/ ac pin was grounded to enable ac coupling. the vpi pin was connected to 3.3 v by shorting it to vps. the alpha of the pulse response filter was set to 0.35. the baseband input power to the ADRF6518 was swept , and the analog gains were adjusted to maintain a target 1.5 v p- p differential signal level on both the i and q outputs . the vga1 analog gain was adjusted to limit its output to 1.5 v p- p (0.75 v p eak on the peak detector output). the f ilter corner was set to 63 mhz , and the digital gains for vga1, vga2, vga3 , and the p ost a mp lifier were set to 15 db , 21 db , 21 db , and 3 db , respectively. several signal bandwidths, signal types, gains, and outpu t levels were tested, in filter mode and in filter bypass mode. it is important to keep the high - pass corner of the output offset compensation loop low compared to the signal bandwidth . the lower the signal bandwidth is, the lower the user must set the hig h- pass corner to e nsure that the minimal amount of the signal is not corrupted. see the applications information section of the adrf6510 and the adrf6516 data sheets for additional information on the effects of settin g the high - pass corner too high in frequency . it is also important to set the filter corner appropriately for the given signal bandwidth. the user must be careful not to set the filter corner too low in an attempt to achieve more reject ion of
ADRF6518 data sheet rev. 0 | page 28 of 40 the out - of - band blocker s, because this can corrupt the data in the signal and degrade the evm. for examples of this, see the applications information section in the adrf6510 and the adrf6516 data sheets. figure 83 also shows this trade - off between f ilter c orner and signal bandwidth. in figure 73 through figure 77 , the x - axis is appropriately labeled in unit s of a voltage ratio , which is defined as 20 log10( x /1 v p-p ) w here x is any number in units of v p - p. this is done because the 100 ? differential baseband source (agilent mxg n5182b) drives the 400 ? differential input impedance of the ADRF6518 . the standard unit of power ratio, dbm, is o nly applicable in a 50 ? system . figure 73 and figure 74 show evm vs. i nput v oltage over different symbol rates in filter mode (f ilter c orner = 63 mhz ) and in filter by pass m ode, respectively. evm is gener ally better for higher symbol rates while in filter bypass mode. this is mainly due to the absence of noise and distortion components that the filter introduces. for the same 80 msps signal, evm impro ves 11 db when switching from a 63 mhz filter corner to filter bypass mode. for the lower symbol rates, the difference in evm between a 63 mhz filter corner and filter bypass mode is negligible. figure 73 . evm vs. input voltage over symbol rates ; filter corner = 63 mhz, qpsk, gain code = 0000000, 1.5 v p- p differential output level maintained figure 74 . evm vs. input voltage over symbol rates ; filter bypass mode, qpsk, gain code = 0000000, 1.5 v p- p differential output level maintained figure 75 and figure 76 show evm vs. i nput voltage over different modulation types at 50 msps in filter mode and in filter bypass mode, respectively . evm improves for the high - order modulation ty pes when the filter is in bypass mode. figure 75 . evm vs. input voltage over modulation type ; filter corner = 63 mhz, qpsk, 50 msps, gain code = 0000000, 1.5 v p- p differential output level maintained figure 76 . evm vs. input voltage over modulation type ; filter bypass mode, qpsk, 50 msps, gain code = 0000000, 1.5 v p- p differential output level maintained 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?40 ?30 ?20 ?10 0 10 20 evm (db) v in (dbv p-p) 11449-079 5msps 10msps 50msps 80msps 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?40 ?30 ?20 ?10 0 10 20 evm (db) v in (dbv p-p) 11449-080 5msps 10msps 50msps 80msps 100msps 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?40 ?30 ?20 ?10 0 10 20 evm (db) v in (dbv p-p) 11449-081 qpsk 16qam 256qam 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?40 ?30 ?20 ?10 0 10 20 evm (db) v in (dbv p-p) 11449-082 qpsk 16qam 256qam
da ta sheet ADRF6518 rev. 0 | page 29 of 40 figure 77 shows evm vs. i nput voltage over various digi tal gain settings. there is about a 1 db spread of evm over the gain settings. figure 77 . evm vs. input voltage over digital gain settings, filter corner = 63 mhz , qpsk, 50 msps , 1.5 v p- p differential output level maintained e vm system measurement an overall evm measurement was completed with the adl5380 iq d emodulator driving the ADRF6518 . the interface between the two parts was dc - coupled. to achieve this, the vicm/ac pin was floated to enable dc coupling mode and the vpi pin on the ADRF6518 was connected to 5 v to accommodate the 3.1 v output common - mode voltage of the adl5380 . the rf carrier frequency applied to the rf input of the adl5380 and the lo frequency were set to 900 mhz , creating a zero intermediate frequency (i/ f) . the alpha of the pulse response filter was set to 0.35. the rf input power to the adl5380 was swept , and the analog gain s on the ADRF6518 were adjusted to maintain a target 1.5 v p- p differential signal level on both the i and q outputs . the vga1 analog gain was adjusted to limit its output to 1.5 v p- p (0.75 v p eak on the peak detector output) . the f ilter corner was set to 63 mhz , and digital gains for vga1, vga2, vga3 , and the p ost a mp li fier were set to 15 db , 21 db , 21 db , and 3 db , respectively . several signal bandwidths, signal types, gains, and output levels were tested, in filter mode and in filter bypass mode. figure 78 shows three different symbol rates: 10 msps , 50 msps, and 80 msps , with the filter enabled . there is a degradation of evm with increasing symbol rate, but at 10 msps, the system achieves better than ? 40 db of evm for about 50 db of the input power range. the degradation of evm at the high input power for figure 78 to figure 83 is caused by the adl5380 compressing. by placing an rf attenuator in front of the adl5380 , the user can extend the dynamic range of the system. figure 78 . evm vs. input power over symbol rate ; qpsk, filter corner = 63 mhz, gain code = 0000000, 1.5 v p- p differential output level maintained figure 79 shows four different symbol rates , with the f ilter in b ypa ss mode. evm generally improves while in filter bypass mode , especially at the higher symbol rates , due to the absence of noise, iq gain mismatch, iq phase mismatch, raw group delay, and group delay mismatch, which are some dominant sources of error that t he filter add s when enabled. figure 79 . evm vs. input power over symbol rate; filter bypass mode, gain code = 0000000, 1.5 v p- p differential output level maintained figure 80 s hows the evm for a 50 msps signal over several different digital modulation types while the filter is in bypass mode. up to 256 qam, there is a n improvement to evm, but this is due to how evm is calculated, rather than absolute symbol error being reduced. (evm is c alculated as the ratio of the rms power of the symbol error vector to the rms average power of the constellation. a similar and perhaps better metric is modulation error ratio, or mer, which is defined as the ratio of the rms power of the ideal symbol to t he rms power of the symbol error vector .) the 1024 qam signal starts to degrade due to the noise and distortion components impacting the closely packed symbols in the constellation. 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?40 ?30 ?20 ?10 0 10 20 evm (db) v in (dbv p-p) 11449-083 9db, 12db, 12db, 3db 12db, 12db, 12db, 3db 15db, 12db, 12db, 3db 15db, 15db, 15db, 3db 15db, 18db, 18db, 3db 15db, 21db, 21db, 3db 15db, 21db, 21db, 9db 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?80 2010 0 ?10?20?30?40?50 ?60?70 evm (db) p in (dbm) 11449-084 10msps 50msps 80msps 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?80 2010 0 ?10?20?30?40?50?60?70 evm (db) p in (dbm) 11449-085 10msps 50msps 80msps 100msps
ADRF6518 data sheet rev. 0 | page 30 of 40 figure 80 . evm vs. input power over digital mod ulation type; filter bypass mode, gain code = 0000000, 1.5 v p- p differential output level maintained figure 81 shows the same four modulation types as in figure 80, but wi th the filter enable d. evm is generally degraded due to filter noise , as described in the noise characteristics section . figure 81 . evm vs . input power over digital modulation type; filt er corner = 63 mhz, gain code = 0000000, 1.5 v p- p differential output level maintained figure 82 shows a sweep over several output setpoints, from 1.5 v p- p to 5 .0 v p- p. evm only changes by a couple of d ecibels f or the full output range tested , which gives the user flexibility in determining the level at which the output signal is maintained . although not shown in figure 82 , signals slightly bigger than 5 v p- p have drasti cally degraded evm , and loss of lock can occur easily. figure 82 . evm vs. input power over output level; filter corner = 63 mhz, qpsk, 50 msps, gain code = 0000000 figure 83 shows the evm for several different digital gain settings. there is an approximate 2 db to 3 db of evm degradation at the following gain settings: vga1 = 9 db, vga2 = 12 db, vga3 = 12 db, and postamplifier = 3 db. this is due to the noise figure of the ADRF6518 increasing with the lower gain setting of vga1 (vga1 sets the noise figure for the part). this correlation is shown in figure 23 , which shows about a 2 db in crease in noise figure when the vga1 digital gain is changed from 15 db to 9 db. figure 83 . evm vs. input power over gain code; filter mode = 63 mhz, qpsk, 50 msps, 1.5 v p- p differential output level maintained 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?80 2010 0 ?10?20?30?40?50?60?70 evm (db) p in (dbm) 11449-086 qpsk 16qam 256qam 1024qam 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?80 2010 0 ?10?20?30?40?50?60?70 evm (db) p in (dbm) 11449-087 qpsk 16qam 256qam 1024qam 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?80 2010 0 ?10?20?30?40?50 ?60?70 evm (db) p in (dbm) 11449-088 1.5v p-p 2.0v p-p 2.5v p-p 3.0v p-p 3.5v p-p 4.0v p-p 4.5v p-p 5.0v p-p 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 ?80 2010 0 ?10?20?30?40?50?60?70 evm (db) p in (dbm) 11449-089 gains: 15db/21db/21db/3db gains: 15db/21db/21db/9db gains: 9db/12db/12db/3db gains: 12db/12db/12db/3db gains: 15db/12db/12db/3db gains: 15db/15db/15db/3db gains: 15db/18db/18db/3db
data sheet ADRF6518 rev. 0 | page 31 of 40 effect of filter bw on evm figure 84 shows how changing the filter bw affects the evm for signals at several different symbol rates. the x-axis is normalized such that it displays the baseband bandwidth of each respective signal to the set filter corner. for example, a filter corner of 10 mhz and a signal with a baseband bandwidth of 5 mhz yields 2 hz/hz. similarly, a filter corner of 50 mhz and a signal with a baseband bandwidth of 25 mhz also yields 2 hz/hz. baseband bandwidth is defined by the following: ?? 2 1) ( ? ?? ? ratesymbol bw bb the general behavior shows that the higher the ratio of the filter corner to baseband bandwidth is, the better the evm. this behavior starts to plateau at around a 2 ratio. this behavior affects the higher bandwidth signal more so than the smaller bandwidth signals. the primary reason for this behavior is that the noise is not flat across frequency (there is some interaction between the filters and all the gain stages). the noise shaping degrades evm as the filter corner starts to encroach well outside of the signal bandwidth. figure 84. evm vs. filter corner/baseband bw ratio over symbol rate, filter corner = 63 mhz, qpsk, 1.5 v p-p output level, ?20 dbm input power pull-down resistors for disable function the ADRF6518 offers a disable function, by pulling enbl low, that brings the supply current to approximately 1 ma. for the function to work correctly, a dc path to ground must be established on the output pins (opp1, opm1, opp2, opm2) to allow proper discharge of the postamplifier. figure 85 shows how to properly place the pull-down resistors. the resistor value must be big enough so that it does not interfere with the output impedance that the postamplifer sees (for example, 400 ), but not so big that it prevents proper discharge, effectively becoming an open circuit. for most applications, a value of r pulldown = 10 k sufficiently satisfies these conditions. instability at high gain in filter bypass mode the user must be cautious while operating the ADRF6518 at the highest of gains in filter bypass mode. due to the high gain (up to 66 db) and wide bandwidth (up to 350 mhz with maximum digital gains), the ADRF6518 is susceptible to oscillations when it is in filter bypass mode and its gain is set above 60 db. the oscillation manifests itself with a broadband rise in the noise floor and significantly degrades the snr and evm. orthogonal input to output signal paths on the printed circuit board (pcb) helps reduce this oscillation. this can be seen in the top layer silkscreen, shown in figure 90. it is recommended that any posts or headers not be placed for measurement purposes on the signal paths, especially the output signal paths. doing so causes the output signal to radiate back to the input and induce the oscillation at even lower gains than 60 db. figure 85. pull-down resistors 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 01 0 987654321 evm (db) filter corner/baseband bandwidth (hz/hz) 11449-090 5msps 10msps 20msps 50msps vpsd comd le clk data sdo/rst vicm/ac vpi c o m i n p 2 i n m 2 v p s v p k v g n 2 o f s 2 v p s e n b l i n p 1 i n m 1 v p s r a v g v g n 1 o f s 1 v p s opp1 opm1 com vgn3 vocm com opm2 opp2 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 11449-201 ADRF6518 i to next stage q to next stage r pulldown r pulldown r pulldown r pulldown
ADRF6518 data sheet rev. 0 | page 32 of 40 linear operation of the ADRF6518 the ADRF6518 has multiple stages per channel. each stage can independently be driven into compression depending on the gain settings and input signal level. there is only access to the input stages (inp1/inm1, inp2/inm2) and the output stages (opp1/opm2, opp2/opm2) ; therefore, the user must infer the signal level at the input and output of each stage from the device under test ( dut ) input signal level and the gain settings, both analog and digital. the maximum recommen d ed signal levels are shown in figure 88 . all signal levels are in v p-p differential. figure 86 . maximum signal levels ; single channel shown 1 1449-200 opp1/opp2 opm1/opm2 vgn3 inp1/inp2 inm1/inm2 vgn1 vgn2 5.0v p-p 2.2v p-p 2.2v p-p 2.6v p-p 3.1v p-p 5.0v p-p
da ta sheet ADRF6518 rev. 0 | page 33 of 40 evaluation board an evaluation board is available for testing the ADRF6518 . evaluation board control software the ADRF6518 evaluation board is controlled through the usb port on a pc. this software enables/disables the dc offset compensation loop and controls the filter corner frequency, the high and l ow p ower mode s, and the minimum and maximum gains for each amplifier in the ADRF6518 . for information about the register map, see table 5 . for information about spi port timing and control, see figure 2 and figure 3 . after the software is downloaded and installed, start the basic user interface to program the filter corner a nd gain values (see figure 87 ). to program the filter corner, pe r form one of the following: ? click the arrow in the frequency corner mhz section of the window, select the desired corner frequency from the menu, and click write selected cutoff frequency to device . ? click frequency +1 mhz or frequency ?1 mhz to increment or decrement the frequency corner in 1 mhz steps from the current frequency corner. to program the filter mode, offset correction, and power mode, mov e the respective slider switch in the upper right corner of the window . to program the maximum gain s of vga1, vga2, vga3 , and the postamplifier , click the vga1 gain db , vga2 gain db , vga3 gain db , and post amp gain db drop - down box es and select the desire d gain. ? the vga1 maximum gain can be set to 9 db, 12 db , or 15 db. ? the vga2 and vga3 maximum gain can be set to 12 db, 15 db, 18 db , or 21 db. ? the postamplifier maximum gain can be set to 3 db or 9 db. when the user clicks the write selected cutoff frequency to device button, a write operation is executed, immediately followed by a read operation. the updated information is displayed in the vga1 gain db , filter corner mhz , vga2 gain db , vga3 gain db , and post amp gain db fields. figure 87 . analog devices ADRF6518 evaluation software 1 1449-072
ADRF6518 data sheet rev. 0 | page 34 of 40 schematics and artwo rk figure 88 . evaluation board schematic 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 ravg vps vgn1 ofs1 vps inm1 enbl inp1 vocm opp2 opp1 opm2 com vgn3 com opm1 inm2 inp2 vps ofs2 vps com vpk vgn2 vpi clk data comd vicm/ac le sdo/rst vpsd ADRF6518 c31 vpsd vps c2 10f 0.1f c4 vpsd vpi 0.1f c18 vocm 0.1f c19 c20 0.1f c3 6 1 t2 2 4 3 c1 10f l2 33h l1 33h vposd vpos legend net name test point sma input/output com comd digital ground analog ground inp2_se 0 r63 dni c56 0 r18 dni c53 0 r17 0 r1 r21 10k le clk data sdo vps c7 c8 c11 0.1f c15 0.1f c13 0 r4 vps open r44 r50 0 r32 0 r49 0 inm2 c10 c9 6 1 t1 2 4 3 inm1 open r43 r48 0 r31 0 r47 0 inp1_se c12 0.1f vps r20 0 r19 0 r41 0 open r39 opp1 opm1_se open r46 open r45 open r37 0.1f c6 0.1f c23 open r6 r36 0 r35 0 r42 0 open r40 opm2_se opp2 open r38 0.1f c24 c22 c21 c17 0.1f vgn3 vps c16 0.1f c14 vgn1 c16 c27 0.1f vps p2 c30 10f vpi r2 0 vicm c5 0.1f 0.1f c34 open vpk c32 0.1f vgn2 0.1f c33 open r15 open r66 dni r68 dni dni c55 r67 dni dni c25 com_1 com_2 p4 vocm vgn3 vgn2 vgn1 vicm 1 3 5 7 2 4 6 8 10 9 vpi r3 0 0.1f 0.1f 0.1f 0.1f tst2 0.1f 0.1f open r5 tst1 0.1f 0.1f 61 t3 2 43 61 t4 2 43 p1 1 2 vpk 1 1449-073
da ta sheet ADRF6518 rev. 0 | page 35 of 40 figure 89 . usb evaluation board schematic 56 55 54 53 52 51 50 49 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 35 36 37 38 39 40 41 42 pd7_fd15 pd4_fd12 pd6_fd14 pd5_fd13 gnd clkout gnd vcc pa5_fifoard1 pa2_sloe reset_n pa3_wu2 pa4_fifoard0 pa6_pktend pa7_flagd_scls_n gnd vcc sda pb4_fd4 pb3_fd3 pb0_fd0 scl pb1_fd1 pb2_fd2 dplus xtalout xtalin rdy1_slwr avcc avcc agnd rdy0_slrd cy7c68013a-56ltxc u4 le 9 dminus 10 agnd 11 vcc 12 gnd 13 ifclk 14 reserved 23 pb5_fd5 24 pb6_fd6 27 vcc 25 pb7_fd7 26 gnd 28 gnd 29 30 31 32 33 34 ctl1_flagb pa1_int1_n ctl0_flaga ctl2_flagc vcc pa0_int0_n 48 47 46 45 44 43 wakeup vcc pd0_fd8 pd1_fd9 pd3_fd11 pd2_fd10 clk data 3v3_usb 3v3_usb 3v3_usb c48 10pf c49 0.1mf 3v3_usb 3v3_usb r61 2k cr2 3v3_usb r64 100k c37 0.1mf c45 0.1mf r62 100k 3v3_usb y1 24 mhz 3 4 2 1 c54 22pf c51 22pf 1 2 3 4 5 g1 g2 g3 g4 5v_usb p5 1 2 3 4 5 6 7 8 a0 a1 a2 gnd sda scl wc_n vcc 3v3_usb 3v3_usb 24lc64-i_sn u2 5v_usb adp3334 u3 1 8 2 3 4 7 6 5 out1 out2 fb nc in2 in1 sd gnd c47 1.0f r65 2k cr1 r69 78.7k c50 1000pf r70 140k c52 1.0f 3v3_usb dgnd c35 0.1f c42 0.1f c36 0.1f c41 0.1f c40 0.1f c44 0.1f c46 0.1f 3v3_usb r60 2k r59 2k c38 10pf c39 0.1f sdo 1 1449-074
ADRF6518 data sheet rev. 0 | page 36 of 40 figure 90 . top layer silkscreen figure 91 . component side layout table 6 . evaluation board configuration options components function default condit ions c1, c2, c4, c11, c12, c15, c16, c30, c31, l1, l2, r2, r3 , p 4 power supply and ground decoupling. nominal supply decoupling consists of a 0.1 f capacitor to ground. c1, c2, c30 = 10 f (size 1210) c4, c11, c12, c15, c16, c31 = 0.1 f (size 0402) l1, l2 = 33 h (size 1812) r2, r3 = 0 (size 0402) p4 = i nstalled t1, t2, c3, c6, c7 to c10, r31, r32, r43, r44, r45, r46, r47, r48, r49, r50 input interface. the inp1 _se , inm1, inp2_se, and inm2 input smas are used to drive the part differentially by bypa ssing the baluns. using only in p1 _se and inp 2 _se in conjunction with the baluns enables single - ended operation. the default configuration of the evaluation board is for single - ended operation. t1 and t2 are 8:1 impedance ratio baluns that transform a singl e- t1, t2 = pulse electronics cx2049 lnl c3, c6 = 0.1 f (size 0402) c7 to c 10 = 0.1 f (size 0602) r31 , r 32, r 47 to r 50 = 0 (size 0402) 1 1449-075 1 1449-076
da ta sheet ADRF6518 rev. 0 | page 37 of 40 components function default condit ions ended signal in a 50 system into a balanced differential signal in a 400 system. r31 , r 32, r 47, r 48, r 49 , and r 50 are populated for appropriate balun interface to bypass the t1 and t2 baluns for differential interfacing, remove the balun interfacing resisto rs , r31 , r 32, r 47, r 48, r 49 , and r 50 , and populate r 43, r 44, r 45 , and r 46 with 0 resistors. r43 to r46 = open (size 040 2 ) t 3 , t 4 , c 19 to c 24 , r5, r6 , r19 , r 20, r35 to r 42 output interface. the opp1, opm1 _se , opp2, and opm2_se output smas are used to obtain differential signals from the part when the output baluns are bypassed. using op m 1_se, opm2_se, and the baluns, the user can obtain single - ended output signals. the default configuration of the evaluation board is for single - ended operation. t3 and t 4 are 8:1 impedance ratio baluns that transform a differential signal in a 400 system into a single - ended signal in a 50 system. to bypass the t3 and t4 baluns for differential interfacing, remove the balun interfacing resistors , r19, r20, r35, r36, r41, and r42, and populate r37, r38, r39, and r40 with 0 resistors. r5 and r6 can be populated with an impedance of at least 400 to terminate the output in differential applications. t3, t4 = pulse electronics cx2049lnl c19 to c2 4 = 0.1 f (size 0402) r5 , r 6 = open (size 0402) r19, r20, r35, r36, r41, r42 = 0 (size 0402) r37 to r 40 = open (size 0402) p2 enable interface. the ADRF6518 is powered up by applying a logic high voltage to the enbl pin (jumper p 2 is connected to vps). p2 = installed for enable p3, r1, r17, r18, r21, r63 , c25, c53, c55, c56 serial control interface. the digital interface sets the corner frequency, vga1/ vga 2/v ga3 maximum gain s, and the postamplifier maximum gain using the serial interface via the le, clk, data, and sdo pins. rc filter networks can be populated on the clk , le , and data lines to filter the spi signals. clk, data, and le signals can be observed via p3 for debug purposes. setting c25, c53, and c56 = 330 pf is recommending for filtering. p3 = installed r1 = 0 (size 0402) r21 = 10 k (size 0402) c25 , c53, c55, c56 = open (size 0402) r17, r18 , r 6 3 = 1 k (size 0402) c13, c14 dc offset compensation loop. the dc offset compensation loop is enabled via the spi port. when enabled, the c13 and c14 capacitors are connected to circuit common. the high - pass corner frequency is expressed as follows: f hp (hz) = 6.7 ( post filter linear gain / c ofs (f)) c13, c14 = 0.1 f (size 0402) c5 input common - mode reference . the input common - mode voltage can be monitor ed at the vicm pin. if the vicm pin is left open, an input common - mode voltage must be supplied externally ( dc coupling mode). if vicm pin is connected t o ground, the input common - mode defaults to vp i /2 (ac coupling mode) . c 5 = 0.1 f (size 0402 ) c18 output common - mode setpoint. the output common - mode voltage can be set externally when applied to the vocm pin. if the vocm pin is left open, the output com mon - mode voltage defaults to vps/ 2. c18 = 0.1 f (size 0402) c17, c27, c32 analog gain control. the range of the analog gain pin s, vgn1, vgn2, and vgn3 , is from 0 v to 1 v, creating a gain scaling of 30 mv/db. c17, c27, c32 = 0.1 f (size 0402) p1, r4, r15 , c 33, c 34 peak d etector. p1 = i nstalled r4 = 0 (size 0402) r15 , c33, c34 = open (size 0402) u2, u 3, u4, p5 cypress m icrocontroller, eeprom, and ldo . u2 = microchip micro 24lc 64 u3 = analog devices adp3334 acpz u4 = cypress semiconductor cy7c68013a-56 lt xc p5 = mini usb connector c35, c36, c40, c 41, c42, c44, c46 3.3 v supply decoupling. several capacitors are used for decoupling on the 3.3 v supply. c35, c36, c40, c 41, c42, c44, c46 = 0.1 f ( 0402)
ADRF6518 data sheet rev. 0 | page 38 of 40 components function default condit ions c37, c38, c39, c45 , c48, c49, r59, r60, r61, r62, r 64, cr 2 cypress and eeprom components. c38, c48 = 10 pf ( 0402) c37, c39, c45, c 49 = 0.1 f ( 0402) r59 , r 60, r 61 = 2 k ( 0402) r62 , r 64 = 100 k ( 0402) cr2 = rohm sml -21 omtt 86 c47, c50, c52, r 65, r 69, r 70, cr1 ldo components . c47, c52 = 1 f ( 0402) c50 = 1000 pf ( 0402) r65 = 2 k ( 0402) r69 = 78.7 k ( 0402) r70 = 140 k ( 0402) cr1 = rohm sml -21 omtt 86 y1 , c51, c54 crystal oscillator and components. 24 mhz crystal oscillator. y1 = ndk nx 3225sa-24 mhz c51, c54 = 22 pf ( 0402)
da ta sheet ADRF6518 rev. 0 | page 39 of 40 outline dimensions figure 92 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very v ery thin quad (cp - 32 - 13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adrf 6518 acpz - r 7 ? 40 c to + 85 c 32 - lead lfcsp_wq, 7 tape and reel cp - 32 - 13 adrf 6518 acpz -wp ?40 c to + 85c 32- lead lfcsp_w q, waffle pack cp-32-13 adrf 6518- evalz evaluation board 1 z = rohs compliant part. 05-24-2012- a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 3.45 3.30 sq 3.15 compliant to jedec standards mo-220- whhd . 3.50 ref
ADRF6518 data sheet rev. 0 | page 40 of 40 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11449 -0- 6/13(0)

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